Veri cation of Arithmetic Circuits Using Binary MomentDiagrams ?

Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented eeciently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, where component modules are rst shown to implement their word-level speciications. The overall circuit functionality is then veriied by composing the component functions and comparing the result to the word-level circuit speciication. Multipliers with word sizes of up to 256 bits have been veriied by this technique .